The present invention relates to a rounding computing method for improving accuracy of a computational result and speeding up an arithmetic operation, using a low-accuracy multiplier at fixed-point arithmetic and a computing device therefor.
A decoder for decoding an MP3 (MPEG-1 Audio Layer 3) corresponding to an audio compression technology has conventionally been in need of high-speed multiplication processing.
FIG. 2 is a diagram showing a flow of processing for decoding a conventional MP3 file. Upon decoding of an MP3, an unillustrated decoder performs dequantization processing (Step S2) for generating matrix data meaningful as a physical quantity on the basis of data read from the MP3 file 1 of 17 binary digits (hereinafter called “bits”)(Step S1). The decoder needs to round elements of each matrix of 17 bits obtained by dequantization to 16-bit data 2 (i.e., bring the same into integer form) (Step S4) in order to input the same to an unillustrated high-speed 16-bit multiplier (Step S3). To this end, the most significant bit (hereinafter called “MSB”) or the least significant bit (hereinafter called “LSB”) of the MP3 file 1 must be discarded. The rounded data is computed by the multiplier (Step S5), which in turn is outputted from the decoder (Step S6).
Incidentally, when the LSB is discarded upon the previously mentioned process of rounding the data to 16 bits (Step S4), the accuracy of the data is deteriorated. On the other hand, when the MSB is discarded, data is rounded to an unintentioned numerical value where the data is used to the MSB in full, so that there is a fear that a decoded sound is distorted.
A method for solving such a rounding problem has been proposed in a conventional patent document 1 (U.S. Pat. No. 6,360,204B1).
FIG. 3 is a diagram showing the rounding computing method described in the conventional patent document 1.
In the present rounding computing method, rounding processing is contrived in the following manner to improve the accuracy of an audio decoder.
A result of multiplication using audio data by a digital signal processor (hereinafter called “DSP”) in which a multiplier factor 3 and a multiplicand 4 are respectively s bits, becomes 2s bits at a maximum. Therefore, the multiplication result is rounded to s bits in the following procedure.
Either upper s bits of the multiplication result 5 or lower s bits thereof to be ensured is first selected. In general, the process of rounding off upper bits is low in rounding accuracy, and the process of rounding off lower bits is high in rounding accuracy. These selecting methods are optional. Next, when the upper s bits are ensured, the presence or absence of saturation of data (that is, whether the data is used up to the MSB) is confirmed (Step S10). If the answer is found to be NO, then rounding processing is executed (Step S11). If the answer is found to be YES, then no rounding processing is done.
According to the conventional computing method, the accuracy of the audio decoded mounted to the s-bit DSP can be improved. There is, however, a problem in that the selectable accuracy is limited to the two types where the upper bits are ensured and the lower bits are ensured as shown in FIG. 3. An application is also limited to the audio decoder.
That is, in the conventional rounding computing method or computing device, for example, a general-purpose microprocessor (hereinafter called “MCU”) encounters difficulties in speeding up multiplication using a low-accuracy multiplier reduced in the number of bits and at the same time selecting and ensuring the accuracy of computational or operational data with flexibility. Further, it was difficult to make it possible to apply a target application without being limited to the audio decoder.